1. Field of the Invention
The present invention relates to a semiconductor memory and the sense amplifier architecture therefore.
2. Description of the Related Art
FIG. 1 illustrates a prior art architecture for a dynamic random access memory (DRAM). As shown, the DRAM 1 includes a plurality of memory banks BANK-1 to BANK-4. Each memory bank BANK-1 to BANK-4 includes a plurality of memory cells MC. A row decoder and column decoder decode an address and enable word lines WL and column select lines CSL to, for example, read data out from the memory cell MC. The data output from the memory cell MC is output to a bit line BL. A bit line sense amplifier BLSA senses (e.g. amplifies) the data value output by the memory cell MC, and outputs the sensed data value on data line DL and complementary data line DLB. A multiplexer MUX1, MUX2, MUX3 and MUX4, associated with a respective one of the memory banks BANK-1 to BANK-4 selectively outputs the data value on the data line DL and complementary data line DLB based on a respectively received bank address BA1-BA4.
Because the size of the BLSAs are small and the data line loading is very large, a data line sense amplifier DSA is used to further amplify the signal on one of the data lines connected to the DSA by one of the multiplexers MUX1-MUX4. Generally, there are two types of DSAs—a voltage sense amplifier VSA and a current sense amplifier CSA. A VSA amplifies a signal to obtain a large voltage swing, and takes a significant amount of time to transition the signal between states. By contrast, when a CSA amplifies a signal less time is taken to transition the signal between states, but the voltage swing is not very large. As such, a CSA has a faster response speed than a VSA, but a VSA produces a greater voltage swing. To obtain the best of both types of amplifiers, the DSA in the prior art architecture of FIG. 1 includes a CSA and VSA.
As shown in FIG. 1, if the number of data pins DQl-DQn is eight, then eight DSAs are provided, which means that eight CSAs are provided. While the response speed of the CSA is greater than a VSA, the CSA consumes a greater amount of power in operation. This disadvantage of CSAs becomes a significant problem for wider data capacity memories because each data pad or data pin (DQ) requires a corresponding CSA.